The HBM3 Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The HBM3 Controller IIP can be implemented in any technology.

The HBM3 Controller IIP core supports the HBM3 protocol standard of draft JEDEC specification version 0.93 and is compatible with DFI-version 4.0 or 5.0 specification Compliant. HBM3 Controller IIP also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

The HBM3 Controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The HBM3 Controller IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.