The SDIO Host IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The SDIO Host IIP can be implementedin any technology.

The SDIO Host IIP core supports the SD Host Controller Specification and supporting standards. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, AXI, OCP, Wishbone, VCI, Avalon PLB, Wishbone, Tilelink orcustom buses.

The SDIO Host IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The SDIO Host IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.