The TileLink to APB Bridge IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The TileLink to APB Bridge IP can be implemented in any technology.

The TileLink to APB Bridge IIP core supports TileLink and APB specification.

The TileLink to APB Bridge IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The TileLink to APB Bridge IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.